1. Field of the Invention
This invention relates to a semiconductor storage device, and is suitably applied to a semiconductor storage device composed of, for example, a dynamic random access memory (DRAM).
2. Description of the Related Art
In conventional semiconductor storage devices, memory cell arrays are provided in such a manner that a plurality of memory cells which are the minimum units of data storage element is arranged in a array structure, a plurality of word lines parallel to a row direction of the memory cells arranged in the array structure and a plurality of bit lines parallel to a line direction are arranged in a lattice pattern, and each memory cell is connected to a word line and a bit line at the crossing position of the word line and bit line.
Further, in such semiconductor storage devices, redundant columns are also provided in such a manner that a plurality of redundant memory cells which is usable instead of broken memory cells is arranged in an array structure on one side in a line direction of a memory cell array, word lines parallel to the row direction (hereinafter, referred to as redundant word lines) and bit lines parallel to the line direction are arranged, and each redundant memory cell is connected to a redundant word line and a bit line at the crossing position of the redundant word line and bit line.
In the semiconductor devices, if a memory cell is broken in a memory cell array, a plurality of redundant memory cells of one row in the array structure is used instead of a plurality of memory cells of one row including the broken memory cell in an array structure. As a result, data can be stored and reproduced by using the same number of memory cells as a plurality of memory cells in the memory cell array if a broken memory cell exists (for example, refer to page 3 in Japanese Patent Laid Open No. 11-120788).
In another kind of semiconductor storage devices which is provided with memory cell arrays in such a manner that a plurality of word lines being connected to a plurality of memory cells and a plurality of redundant word lines being connected to a plurality of redundant memory cells are wired next to each other in a line direction, use of redundant memory cells, so-called a shift-redundancy method is applied. In this method, row addresses from a row address assigned to a word line being connected to a broken memory cell to a row address assigned to a word line next to a redundant word line are reassigned to other word lines and redundant word lines by sequentially shifting them in a line direction in a unit of even number of row addresses. Thereby a plurality of redundant memory cells being connected to the redundant word lines is made usable, instead of a plurality of memory cells including the broken cell being connected to the word line.
In addition, recently, with the progresses of semiconductor fine processing techniques, a floating capacity reducing method called a twisted-bit line architecture has been proposed for semiconductor storage devices employing the shift-redundancy method. As shown in FIG. 1, two bit lines BL1A and BL1B, BL2A and BL2B, . . . , BLNA and BLNB in order in a row direction shown in an arrow R are designated to operate in a pair as bit line pairs BL1, BL2, . . . , BLN in a memory cell array MSA1, and the two bit lines BL1A and BL1B, BL3A and BL3B of the bit line pairs BL1, BL3, . . . are switched once or plural times in a line direction, so as to reduce floating capacity between the twisted bit line pairs BL1, BL3, . . . and their neighboring bit line pairs BL2, . . . , BLN, resulting in avoiding interference noise which is caused by capacity connection between the bit line pairs BL1, BL2, BL3, . . . , BLN.
In this connection, in the semiconductor storage devices having the above structure, two memory cells MS out of a plurality of memory cells MS of one line are arranged in each region (hereinafter, referred to as a memory cell region) surrounded by a bit line pair BL1, . . . , BLN and two word lines WL1 and WL2, . . . , WLN-1 and WLN, WLT1 and WLT2, . . . .
In each memory cell region having the bit line pairs BL1, . . . , BL1N of which the wire positions of the two bit lines BL1A and BL1B, . . . , BLNA and BLNB are not switched, (hereinafter, these parts are referred to as wire position nonswitching parts NCAR1 to NCAR4), that is, in each memory cell from the input/output stages of the bit line pairs BL1, . . . , BL1N till the twisting positions, one memory cell MS is connected to one bit line BL1, . . . , BLNA and one word line WL1, . . . , WLN-1, WLT1 and the other memory cell MS is connected to the other bit line BL1B, . . . , BLNB and the other word line WL2, . . . , WLN, WLT2, . . . .
In addition, in each memory cell having the bit line pairs BL1, . . . , BL1N of which the wire positions of the two bit lines BL1A and BL1B, BL3A and BL3B, . . . are switched by twist (hereinafter, these parts are referred to as wire position switching parts CCAR1 and CCAR2), one memory cell MS is connected to the other bit line BL1B, BL3B, . . . and one word line WL1, . . . , WLN-1, WLT1, . . . , and the other memory cell MS is connected to one bit line BL1A, BL3A, . . . , and the other word line WL2, . . . , WLN, WLT2, . . . .
For the semiconductor storage devices employing the shift-redundancy method and the twisted-bit line architecture, an evaluation test of data dependency called pattern sensitive in each memory cell MS has been also proposed. This test is conducted in manufacturing in such a manner that, as shown in FIG. 2, evaluation test data of level “0”, “1” is stored in the memory cells MS of the memory cell array MSA1 in a prescribed storing pattern selected depending on the physical arrangement of the memory cells MS, for example, checkerwise, and are reproduced, and then the level of the evaluation test data before storage are compared with the level of the evaluation test data reproduced.
In such semiconductor storage devices, however, evaluation test data cannot be stored in the memory cells MS in a previously selected storing pattern easily. This is because, as shown in FIG. 3, when evaluation test data of level “0”, “1” for evaluation test of data dependency, which are entered from the outside, are given to, for example, one-sided bit lines BL1A, . . . , BLNA of the bit line pairs BL1, . . . , BLN, the evaluation test data are stored in one-sided memory cells MS out of the one- and the other-sided memory cells MS in the wire position nonswitching parts NCAR1 to NCAR4 of the bit line pairs BL1, BL3, . . . . In the wire position switching parts CCAR1 and CCAR2, however, the evaluation test data are stored in the other-sided memory cells MS with, for example, inverting the level of the data in the wire position switching parts CCAR1 and CCAR2.
Therefore, for such semiconductor storage devices, such method is considered that row addresses assigned to the word lines crossing the wire position switching parts CCAR1 and CCAR2 of the bit line pairs BL1, . . . , BLN are stored in advance, and the evaluation test data are given to the bit line pairs BL1, . . . , BLN after inverting the level of the evaluation test data when a row address is specified for storing the evaluation test data from the outside.
The semiconductor storage devices employing this method have also a problem in that the evaluation test data cannot be stored in the memory cells MS in a storing pattern easily. This is because, as shown in FIG. 4, when row addresses assigned to word lines WLN-1, WLN, WLT1, WLT2, . . . are shifted over twisting positions in a line direction shown by an arrow K in a unit of even number of row addresses by performing shift-redundancy process due to the detection of a broken memory cell BMS, the word lines WLN-1, WLN, WLT1, WLT2, . . . crossing the wire position switching parts CCAR1 and CCAR2 cannot be specified based on the pre-stored row addresses correctly.